Local measurement record — 2026-09-22

Historical v1 data, withdrawn as performance evidence. CPU 2/3 are SMT siblings, not different physical cores. The one-way TSC experiment did not validate cross-thread clock offsets, and the MPMC benchmark added a global per-message RMW counter. Payloads, capacity and placement also differ from the revised experiment. Do not interpret new numbers as a speedup over v1. See revised-benchmark.txt and RESEARCH.md for the revised methodology.

Environment:

CPU: AMD Ryzen 5 9600X, 6 cores / 12 logical processors
OS: Windows (the host used for this repository session)
Compiler: Zig 0.15.2 zig c++, C++20, -O3
Affinity: producer on logical CPU 2, consumer on logical CPU 3 for SPSC; MPMC workers pinned to distinct logical CPUs where available
No real-time scheduling and no isolated cores

Correctness run:

spsc: strict order OK (1000000 messages)
mpmc: no loss/duplicate OK (1000000 messages)
book: stale/gap detection OK
updates=1000000 gaps=0 orders=500000

Five SPSC runs after warm-up:

p50 TSC ticks: 154, 154, 154, 154, 154
p99 TSC ticks: 193, 193, 193, 193, 193
p99.9 TSC ticks: 232, 193, 232, 193, 232
throughput Mmsg/s: 505.28, 497.38, 489.36, 489.09, 470.74

Three bounded MPMC runs:

1P/1C Mmsg/s: 50.50, 49.65, 49.72
2P/2C Mmsg/s: 41.22, 41.51, 41.28
4P/4C Mmsg/s: 19.27, 19.28, 19.50

The SPSC maximum ranged from 91,687 to 384,382 TSC ticks despite stable p99. The source of those outliers was not established by scheduler/interrupt traces. Linux perf counters and the journal runtime have not been collected. The journal was cross-compiled for x86_64 Linux, which does not validate runtime I/O.